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p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 1 of 18 evb description rev. 003 jan/08 features ! dual rf input for antenna space and frequency dive rsity, lna cascading or differential feeding ! fully integrated pll-based synthesizer ! 2 nd mixer with image rejection ! reception of ask or fsk modulated signals ! wide operating voltage and temperature ranges ! very low standby current consumption ! low operating current consumption ! internal if filter ! internal fsk demodulator ! average or peak detection data slicer mode ! rssi output with high dynamic range for rf level indication ! output noise cancellation filter ! mcu clock output ! high over-all frequency accuracy ordering information part no. (see paragraph 4) EVB71121-315-c EVB71121-868-c EVB71121-433-c EVB71121-915-c note 1: peak detection mode is default population. application examples ! general digital and analog rf receivers at 300 to 930mhz ! tire pressure monitoring systems (tpms) ! remote keyless entry (rke) ! low power telemetry systems ! alarm and security systems ! active rfid tags ! remote controls ! garage door openers ! home and building automation general description the mlx71121 is a multi-band, single-channel rf re ceiver based on a double-conversion super-heterodyne architecture. it can receive fsk and ask modulated signals. the ic is designed for general purpose applications for example in the european bands at 433mhz and 868mhz or for similar applications in north america or asia, e.g. at 315mhz or 915mhz. the receiver?s extended temperature and supply voltage r anges make the device a perfect fit for automotive or similar applications where harsh environmental conditions are expected.
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 2 of 18 evb description rev. 003 jan/08 document content 1 theory of op eration ................................................................................................... 3 1.1 general........................................................................................................................ ..... 3 1.2 technical data overview.................................................................................................. 3 1.3 block diagram .................................................................................................................. 4 1.4 operating modes .............................................................................................................. 5 1.5 frequency range ............................................................................................................. 5 1.6 lna selection.................................................................................................................. . 5 1.7 demodulation selection.................................................................................................... 5 1.8 data slicer .................................................................................................................... .... 5 2 frequency planning ................................................................................................... 6 2.1 calculation of frequency settings.................................................................................... 7 2.2 standard frequency plans ............................................................................................... 8 2.3 433/868mhz frequency diversity .................................................................................... 8 3 dual-channel application circui ts for fsk & ask recep tion ............................... 9 3.1 peak detector data slicer ................................................................................................ 9 3.1.1 component arrangement top side (peak detection da ta slicer) ............................................ 10 3.2 averaging data slicer configured for-bi phase codes .................................................. 11 3.2.1 component arrangement top side (averaging data slicer) .................................................... 12 3.3 component list for antenna space diversity ................................................................. 13 3.4 pcb layouts for antenna space diversity ..................................................................... 14 4 board va riants.......................................................................................................... 14 5 package descr iption ................................................................................................ 15 5.1 soldering information ..................................................................................................... 15 6 reliability in formation ............................................................................................. 16 7 esd precau tions ...................................................................................................... 16 8 disclai mer ................................................................................................................. 18
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 3 of 18 evb description rev. 003 jan/08 1 theory of operation 1.1 general the mlx71121 receiver architecture is based on a double-conversion super-heterodyne approach. the two lo signals are derived from an on-chip integer-n pll frequency synthesizer. t he pll reference frequency is derived from a crystal (xtal). as the first intermediate frequency (i f1) is very high, a reasonably high degree of image rejection is provided even without using an rf front-end f ilter. at applications asking for very high image rejections, cost-efficient rf front-end filtering can be realiz ed by using a saw filter in front of the lna. the second mixer mix2 is an image-reject mixer. the receiver signal chain is setup by one (or two) lo w noise amplifier(s) (lna1, lna2), two down-conversion mixers (mix1, mix2), an on-chip if filter (iff) as well as an if amplifier (ifa). by choosing the required modulation via an fsk/ask switch (at pin modsel), ei ther the on-chip fsk demodulator (fsk demod) or the rssi-based ask detector is selected. a second order data filter (oa1) and a data slicer (oa2) follow the demodulator. the data slicer threshold can be generated from the mean-value of the data stream or by means of the positive and negative peak detectors (pkdet+/-). a digital post-processing of the sliced data signal can be performed by a noise filter (nf) building block. the dual lna configuration can be used for antenna s pace diversity or antenna fr equency diversity or to setup an lna cascade (to further improv e the input sensitivity). the two ln as can also be setup to feed the rf signal differentially. a sequencer circuit (seq) controls the timing during start-up. this is to reduce start-up time and to minimize power dissipation. a clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a microcontroller. the clock output is open collector and gets activated through a load connected to positive supply. 1.2 technical data overview ! input frequency ranges: 300 to 470mhz 610 to 930mhz ! power supply range: 2.1 to 5.5v ! temperature range: -40 to +125c ! shutdown current: 50 na ! operating current: 10.0 to 11.1ma ! internal if: 1.8mhz with 300khz 3db bandwidth ! fm/fsk deviation range: 10khz to 100khz ! image rejection: 65db 1 st if (with external rf front-end filter) 25db 2 nd if (internal image rejection) ! maximum data rate: 50kps rz (bi-phase) code, 100kps nrz ! spurious emission: < -54dbm ! linear rssi range: > 60db ! crystal reference frequency: 16 to 27mhz ! mcu clock frequency: 2.0 to 3.4mhz ! input sensitivity: at 4kbps nrz, ber = 310 -3 frequency 315 mhz 433 mhz 868 mhz 915 mhz fsk internal if2=1.8mhz, 300khz bw, f = 20khz -107dbm -107dbm -104dbm -102dbm ask internal if2=1.8mhz, 300khz bw -112dbm -112dbm -108dbm -105dbm note: - sensitivities given for rf input 1 (without saw filter) - sensitivity for rf input 2 is about 2 to 3db worse (because of saw filter loss)
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 4 of 18 evb description rev. 003 jan/08 1.3 block diagram fig. 1: mlx71121 block diagram the mlx71121 receiver ic consists of the following building blocks: ? pll synthesizer (pll synth) to generate the firs t and second local oscillator signals lo1 and lo2. the pll synth consists of a fully integrated voltage-controlled osc illator (vco), a distributed feedback divider chain (n1, n2), a phase-frequency detector (p fd) a charge pump (cp), a loop filter (lf) and a crystal-based reference oscillator (ro). ? two low-noise amplifiers (lna) for high-sensitivity rf signal reception ? first mixer (mix1) for down-conversion of the rf signal to the first if (intermediate frequency) ? second mixer (mix2) with image rejection for dow n-conversion from the first to the second if ? if filter (iff) with a 1.8mhz center frequency and a 300khz 3db bandwidth ? if amplifier (ifa) to provide a high voltage gain and an rssi signal output ? fsk demodulator (fsk demod) ? operational amplifiers oa1 and oa2 for low- pass filtering and data slicing, respectively ? positive (pkdet+) and negativ e (pkdet-) peak detectors ? switches sw1 to select between fsk and ask as well as sw2 to chose between averaging or peak detection mode. ? noise cancellation filter (ncf) ? sequencer circuit (seq) and biasing (bias) circuit ? clock output (div8) lnai1 lnai2 lnasel vcc mix1 mixn mixp ifa lo2 lo1 lna2 mixo lna1 slcsel roi clko df1 iff ro vco n2 counter n1 counter pfd lf cp div 8 fsk demod modsel pkdet+ pkdet _ 25 4 6 3 vee 2 vee 7 1 lnao2 lnao1 28 5 8 30 32 test 26 rfsel 31 15 14 rssi 24 ifsel 27 13 12 vee 11 10 9 df2 oa1 16 17 bias seq enrx ncf oa2 vcc 22 slc 19 a sk fsk sw1 sw2 100k 100k 100k 100k 100k dtao 29 cint 23 dfo pdp pdn 18 20 21 mix2
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 5 of 18 evb description rev. 003 jan/08 1.4 operating modes enrx description 0 shutdown mode 1 receive mode note: enrx is pulled down internally. 1.5 frequency range two different receive frequency ranges can be selected by the control signal rfsel. rfsel description 0 input frequency range 300 to 470mhz 1 input frequency range 610 to 930mhz 1.6 lna selection lnasel description 0 lna1 active, lna2 shutdown hi-z lna1 and lna2 active 1 lna1 shutdown, lna2 active note: hi-z state means pin lnasel is left floating (pin is internally pulled to v cc /2 in this case). 1.7 demodulation selection modsel description 0 ask demodulation 1 fsk demodulation 1.8 data slicer slcsel description 0 averaging detection mode 1 peak detection mode
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 6 of 18 evb description rev. 003 jan/08 2 frequency planning because of the double conversion archit ecture that employs two mixers and two if signals, there are four different combinations for injecting the lo1 and lo2 signals: lo1 high side and lo2 high side: receiving at f rf (high-high) lo1 high side and lo2 low side: receiving at f rf (high-low) lo1 low side and lo2 high side: receiving at f rf (low-high) lo1 low side and lo2 low side: receiving at f rf (low-low) as a result, four different radio frequencies (rfs) c ould yield one and the same second if (if2). fig. 2 shows this for the case of receiving at f rf (high-high). in the example of fig. 2, the image signals at f rf (low- high) and f rf (low-low) are suppressed by the bandpass characte ristic provided by the rf front-end. the bandpass shape can be achieved either with a saw filter (featuring just a couple of mhz bandwidth), or by the tank circuits at the lna input and output (this typically yields 30 to 60mhz bandwidth). in any case, the high value of the first if (if1) helps to suppress the image signals at f rf (low-high) and f rf (low-low). the two remaining signals at if1 resulting from f rf (high-high) and f rf (high-low) are entering the second mixer mix2. this mixer features image rejection with so-called single-sideband (ssb) selection. this means either the upper or lower sideband of if1 can be selected. in the example of fig. 2, lo2 high-side injection has been chosen to select the if2 signal resulting from f rf (high-high). fig. 2: the four receiving frequencies in a double conversion superhet receiver it can be seen from the block diagram of fig. 1 that there is a fixed relationship between the lo signal frequencies (f lo1 , f lo2 ) and the reference oscillator frequency f ro . lo2 1 lo1 f n f ? = ro 2 lo2 f n f ? = the operating frequency of the internal if filter (iff) and fsk demodulator (fsk demod) is 1.8mhz. therefore the second if (if2) is set to 1.8mhz as well. f lo2 f lo2 f lo1 f rf f rf f rf f rf
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 7 of 18 evb description rev. 003 jan/08 2.1 calculation of frequency settings the receiver has two predefined receive frequency plans which can be selected by the rfsel control pin. depending on the logic level of rfsel pin the sideband selection of the second mixer and the counter settings for n 1 and n 2 are changed accordingly. (see in 1.5) rfsel injection f rfmin [mhz] f rfmax [mhz] n 1 n 2 0 high-low 300 470 4 6 1 low-high 610 930 2 12 the following table shows the relationships of seve ral internal receiver frequencies for the two input frequency ranges. f rf [mhz] f if1 f lo1 f lo2 f ro 300 to 470 1 n f n f 1 if2 1 rf ? + 1 n ) f (f n 1 if2 rf 1 ? + 1 n f f 1 if2 rf ? + 1) (n n f f 1 2 if2 rf ? + 610 to 930 1 n f n f 1 if2 1 rf + ? 1 n ) f (f n 1 if2 rf 1 + + 1 n f f 1 if2 rf + + 1) (n n f f 1 2 if2 rf + + given if2 = 1.8mhz and the corresponding n 1 , n 2 counter settings, above equati ons can be transferred into the following table. f rf [mhz] f if1 f lo1 f lo2 f ro 300 to 470 3 7.2mhz f rf + 3 ) 1.8mhz 4(f rf + 18 1.8mhz f rf + 610 to 930 3 3.6mhz f rf ? 3 ) 1.8mhz 2(f rf + 3 1.8mhz f rf + 36 1.8mhz f rf +
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 8 of 18 evb description rev. 003 jan/08 2.2 standard frequency plans if2 = 1.8mhz. rfsel f rf [mhz] f if1 [mhz] f lo1 [mhz] f lo2 [mhz] f ro [mhz] 315 107.40 422.40 105.60 17.600000 0 433.92 147.04 580.96 145.24 24.206667 868.3 288.23 580.07 290.03 24.169444 1 915 303.80 611.20 305.60 25.466667 2.3 433/868mhz frequency diversity the receiver?s multi-band functionality can be used to operate at two different frequency bands just by changing the logic level at pin rfsel and without c hanging the crystal. this feature is applicable for common use of the 433 and 868mhz bands. below table shows the corresponding frequency plans. if2 = 1.8mhz. rfsel f rf [mhz] f if1 [mhz] f lo1 [mhz] f lo2 [mhz] f ro [mhz] 0 433.25 146.82 580.07 145.02 1 868.3 288.23 580.07 290.03 24.169444
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 9 of 18 evb description rev. 003 jan/08 3 dual-channel application circuits for fsk & ask reception 3.1 peak detector data slicer fig. 3: circuit schematic 2 3 1 2 3 1 mlx71121 17 18 19 20 21 22 23 24 9 1011121314 1516 8 1 2 3 4 5 6 7 32l qfn 5x5 vcc rfsel vee ifap ifan modsel slcsel df2 rssi dfo df1 dtao slc pdp vcc pdn mixn mixp lnai1 clko test roi ifsel lnao2 lnao1 lnai2 mixo vee vee 32 30 29 28 27 25 31 26 enrx cint vcc vcc vcc cb3 c4 c5 c6 l2 cb1 cb2 cf1 crs enrx cf2 xtal cx cro dtao 2 1 clko 4 3 roi 6 5 rssi 8 7 vcc gnd 2 1 4 5 3 cb0 sclsel cp2 cp1 cf3 rcl lna1 lna2 jumpers 0 jumper pads rfsel a sk fsk j umpers 50 c3 l1 50 l3 4 6 1 3 c7 sawfil c8 l4
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 10 of 18 evb description rev. 003 jan/08 3.1.1 component arrangement top side (peak detection data slicer) fig. 4: pcb top-side view
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 11 of 18 evb description rev. 003 jan/08 3.2 averaging data slicer configured for bi-phase codes fig. 5: circuit schematic 2 3 1 mlx71121 17 18 19 20 21 22 23 24 9 1011121314 1516 8 1 2 3 4 5 6 7 32l qfn 5x5 vcc rfsel vee ifap ifan modsel slcsel df2 rssi dfo df1 dtao slc pdp vcc pdn mixn mixp lnai1 clko test roi ifsel lnao2 lnao1 lnai2 mixo vee vee 32 30 29 28 27 25 31 26 enrx cint vcc vcc vcc cb3 c4 c5 c6 l2 cb1 cb2 cf1 rcl cf3 crs enrx 2 3 1 cf2 xtal cx dtao 2 1 csl clko 4 3 roi 6 5 rssi 8 7 vcc gnd 2 1 4 5 3 cb0 sclsel cro lna1 lna2 j umpers rfsel 0 jumper pads a sk fsk j umpers 50 c3 l1 50 l3 4 6 1 3 c7 sawfil l4 c8
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 12 of 18 evb description rev. 003 jan/08 3.2.1 component arrangement top side (averaging data slicer) fig. 6: pcb top-side view
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 13 of 18 evb description rev. 003 jan/08 3.3 component list for antenna space diversity below table is for all application ci rcuits shown in figures 3.1 and 3.2 part size value @ 315 mhz value @ 433.92 mhz value @ 868.3 mhz value @ 915 mhz tol. description c3 0603 100 pf 100 pf 100 pf 100 pf 5% lna input filtering capacitor c4 0603 4.7 pf 3.9 pf 2.2 pf 1.5 pf 5% lna output tank capacitor c5 0603 100 pf 100 pf 100 pf 100 pf 5% mix1 positive input matching capacitor c6 0603 100 pf 100 pf 100 pf 100 pf 5% mix1 negative input matching capacitor c7 0603 nip nip 3.9 pf nip 5% matching capacitor c8 0603 nip nip 1.0 pf nip 5% matching capacitor cb0 0805 33 nf 33 nf 33 nf 33 nf 10% decoupling capacitor, cb1 0603 330 pf 330 pf 330 pf 330 pf 10% decoupling capacitor, cb2 0603 330 pf 330 pf 330 pf 330 pf 10% decoupling capacitor, cb3 0603 330 pf 330 pf 330 pf 330 pf 10% decoupling capacitor, cf1 0603 680 pf 680 pf 680 pf 680 pf 10% data low-pass filter capacitor, for data rate of 4 kbps nrz cf2 0603 330 pf 330 pf 330 pf 330 pf 10% data low-pass filter capacitor, for data rate of 4 kbps nrz value according to the date rate cf3 0603 connected to ground if noise filter not used 10% optional capacitance for noise filter cp1 0603 33 nf 33 nf 33 nf 33 nf 10% pkdet positive filtering capacitor, for data rate of 4 kbps nrz cp2 0603 33 nf 33 nf f 33 nf 33 nf 10% pkdet negative filtering capacitor, for data rate of 4 kbps nrz crs 0603 1 nf 1 nf 1 nf 1 nf 10% rssi output low pass capacitor, for data rate of 4 kbps nrz cro 0603 1 nf 1 nf 1 nf 1 nf 5% optional capacitor, to couple external ro signal 100 nf 100 nf 100 nf 100 nf csl 0603 for averaging detection mode only 10% data slicer capacitor, for data rate of 4 kbps nrz cx 0603 27 pf 27 pf 27 pf 27 pf 5% crystal series capacitor l1 0603 56 nh 27 nh 0 0 5% matching inductor l2 0603 27 nh 15 nh 3.9 nh 3.9 nh 5% lna output tank inductor l3 0603 0 68 nh 22 nh 0 5% matching inductor l4 0603 56 nh 82 nh 22 nh 0 5% matching inductor rcl 0603 3.3 k 3.3 k 3.3 k 3.3 k 5% optional clk output resistor, to clock output signal generated saw fil smd 3x3 safdc315m sm0t00 (315 mhz) safcc433m bl0x00 (433.92 mhz) safcc868m sl0x00 (868.3 mhz) safcc915m al0n00 (915 mhz) low-loss saw filter from murata or equivalent part 17.60000 mhz 24.206667 mhz 24.169444 mhz 25.46667 mhz xtal smd 5x3.2 20ppm cal., 30ppm temp. fundamental-mode crystal note: nip ? not in place, may be used optionally
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 14 of 18 evb description rev. 003 jan/08 3.4 pcb layouts for antenna space diversity ? board layout data in gerber format is available, board size is 32.4mm x 44.5mm. 4 board variants type frequency/mhz modulation board execution EVB71121 ?315 ?fsk according to section 3.1 / 3.2 ?a antenna version ?433 ?ask according to section 3.1 / 3.2 ?c connector version ?868 ?fm ?915 note: available evb setups pcb top view pcb bottom view vcc gnd gnd rfi2 lna sel rfi1 enrx rssi roi clko gnd gnd gnd mod sel melexis dtao lna1 lna2 gnd vcc fsk ask
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 15 of 18 evb description rev. 003 jan/08 5 package description the device mlx71121 is rohs compliant. fig 5: 32l qfn 5x5 quad all dimension in mm d e d2 e2 a a1 a3 l e b min 4.75 4.75 3.00 3. 00 0.80 0 0.3 0.18 max 5.25 5.25 3. 25 3.25 1.00 0.05 0.20 0.5 0.50 0.30 all dimension in inch min 0.187 0.187 0.118 0. 118 0.0315 0 0.0118 0.0071 max 0.207 0.207 0. 128 0.128 0.0393 0.002 0.0079 0.0197 0.0197 0.0118 5.1 soldering information ? the device mlx71121 is qualified for msl3 with soldering peak temperature 260 deg c according to jedec j-std-20 a3 a a1 1 8 24 17 16 9 32 25 d e e b l d2 e2 exposed pad the ?exposed pad? is not connected to internal ground, it should not be connected to the pcb.
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 16 of 18 evb description rev. 003 jan/08 6 reliability information this melexis device is classified and qualified regar ding soldering technology, solderability and moisture sensitivity level, as defined in this specification, accord ing to following test methods: reflow soldering smd?s (s urface m ount d evices) ? ipc/jedec j-std-020 ?moisture/reflow sensitivity classification fo r nonhermetic solid state surface mount devices (classification reflow profiles according to table 5-2)? ? eia/jedec jesd22-a113 ?preconditioning of nonhermetic surface mount device s prior to reliability testing (reflow profiles according to table 2)? wave soldering smd?s (s urface m ount d evices) and thd?s (t hrough h ole d evices) ? en60749-20 ?resistance of plastic- encapsulated smd?s to combined effect of moisture and soldering heat? ? eia/jedec jesd22-b106 and en60749-15 ?resistance to soldering temperat ure for through-hole mounted devices? iron soldering thd?s (t hrough h ole d evices) ? en60749-15 ?resistance to soldering temperat ure for through-hole mounted devices? solderability smd?s (s urface m ount d evices) and thd?s (t hrough h ole d evices) ? eia/jedec jesd22-b102 and en60749-21 ?solderability? for all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with melexis. the application of wave soldering for smd?s is allow ed only after consulting melexis regarding assurance of adhesive strength between device and board. melexis is contributing to global env ironmental conservation by promoting lead free solutions. for more information on qualification of rohs compliant products (rohs = european directive on the restriction of the use of certain hazardous substances) please visit the quality page on our website: http://www.melexis.com/quality_leadfree.aspx 7 esd precautions electronic semiconductor products are sensit ive to electro static discharge (esd). always observe electro static discharge control procedures whenev er handling semiconductor products.
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 17 of 18 evb description rev. 003 jan/08 your notes
p r e l i m i n a r y EVB71121 300 to 930mhz receiver evaluation board description 39012 71121 01 page 18 of 18 evb description rev. 003 jan/08 8 disclaimer 1) the information included in this documentation is subject to melexis intellectual and other property rights. reproduction of information is permissible only if the information will not be altered and is accompanied by all associated conditions, limitations and notices. 2) any use of the documentation wit hout the prior written consent of me lexis other than the one set forth in clause 1 is an unfair and deceptive business practice. melexis is not responsible or liable for such altered documentation. 3) the information furnished by melexis in this docum entation is provided ?as is ?. except as expressly warranted in any other applicable license agreement, mele xis disclaims all warranties either express, implied, statutory or otherwise including but not limited to the merc hantability, fitness for a particular purpose, title and non-infringement with regard to the content of this documentation. 4) notwithstanding the fact that melexis endeavors to take care of the concept and content of this documentation, it may include technical or factual inaccuracies or typographical errors. melexis disclaims any responsibility in connection herewith. 5) melexis reserves the right to change the documentat ion, the specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with melexis for current information. 6) melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in c onnection with or arising out of the furnishing, performance or use of the information in this documentation. 7) the product described in this documentation is intended for use in normal commercial applications. applications requiring operation beyond ranges specif ied in this documentation, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended wit hout additional processing by melexis for each application. 8) any supply of products by melexis will be gov erned by the melexis terms of sale, published on www.melexis.com . ? melexis nv. all rights reserved. for the latest version of this document, go to our website at: www.melexis.com or for additional information contact melexis direct: europe, africa: americas: asia: phone: +32 1367 0495 phone: +1 603 223 2362 phone: +32 1367 0495 e-mail: sales_europe@melexis.com e-mail: sales_usa@melexis.com e-mail: sales_asia@melexis.com iso/ts 16949 and iso14001 certified

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